1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to an improved process for forming a metallization layer having optimally sized barrier and silicide layers.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas as well as field areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the active areas and routing interconnect material between active areas is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application, and is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization structure has also increased.
Each level of metallization incorporates specific materials to enhance contact resistivity and adherence to underlying films/substrate. The low resistivity of aluminum, excellent adherence to both silicon and silicon dioxide, and the low ohmic contact aluminum makes to silicon assures it as an attractive conductor for use in a multilayer metallization scheme. Aluminum can be easily deposited on silicon using conventional techniques such as evaporation or sputtering. Unfortunately, with the advent of high density integrated circuits having thinner diffusion junctions, some of the other properties of aluminum have prevented its applicability as the sole metallization composition. The adherence of aluminum to silicon and silicon dioxide dictates a relatively high solubility of silicon in aluminum at elevated temperatures. The grain boundaries of aluminum thin films provide an avenue through which underlying silicon can diffuse at temperatures above, for example, 400.degree. C. The diffusivity of silicon in aluminum can result in what is often called "junction spiking". Junction spiking refers to voiding of silicon and movement of aluminum into the voided silicon at the junction region thereby causing, in the extreme, aluminum penetration completely through the shallow junction. Complete aluminum penetration can therefore lead to shorting of the junction.
In order to avoid problems of junction spiking, aluminum may be deposited saturated with silicon. The saturated aluminum is thereby rendered unable to absorb substantial amount of additional silicon when contacted with the substrate. Although saturated aluminum minimizes junction spiking, it often generates other problems. For example, saturated aluminum causes nucleation and growth of silicon precipitates from the saturated aluminum material during cooling cycles associated with wafer fabrication. Such precipitation occurs at the contact between the saturated aluminum and the underlying silicon and consists primarily of p-type silicon (since aluminum is a p-type dopant in silicon) doped with aluminum to a fairly high concentration level. P-type precipitates formed at the interface of an n-type junction undesirably increases the contact resistance of that junction. For small n-type contact areas, the increase in resistivity attributed to those precipitates can be sufficient to render a low voltage circuit inoperable.
More recent studies in contact technology have generally drawn away from saturated aluminum as a mechanism for alleviating junction spiking. Researchers have begun to focus upon using what is often called "diffusion barriers". A diffusion barrier is defined as part of the metallization scheme, and comprises a layer of material interposed between an overlying conductor such as aluminum (Al) and an underlying contact region such as doped silicon (Si) or doped/undoped dielectric. The overall structure is therefore a multi-layer structure. The role of a diffusion barrier is to prevent or at least retard interdiffusion of material on opposite sides of the barrier into one another. Thus, an optimal diffusion barrier is one which lessens interdiffusion between materials on opposite sides of the barrier, is stable in the presence of those materials, demonstrates low contact resistivity at the junction of those materials, and has coefficients of thermal expansion compatible with each material.
There are many types of diffusion barriers, including passive barriers, sacrificial barriers, and stuffed barriers. A typical stuffed barrier is a sputter-deposited titanium-tungsten material interposed between the contact region and overlying Al. Sacrificial barriers include interposed polysilicon or titanium (Ti) layers. Recent literature has demonstrated the advantages of passive barriers over conventional stuffed or sacrificial barriers, and generally point to the use of titanium nitride (TiN) as the passive barrier material of choice. See, e.g., U.S. Pat. No. 5,043,300 to Nulman; U.S. Pat. No. 5,278,099 to Maeda; and, U.S. Pat. No. 4,998,157 to Yokoyama et al. (herein incorporated by reference).
Most passive barriers use TiN as the barrier coupled to the substrate material via a Ti layer. The Ti layer is used to reduce contact resistivity of the overall TiN/Ti structure. When TiN is used as the diffusion barrier between Ti and Al, the thermal stability of the contact metallization is reported as being very good. See, e.g., Wolfe, Silicon Processing for VLSI Era; Vol. 2; Process Integration, (Lattice Press, 1990), pp. 132-133 (herein incorporated by reference). According to many conventional techniques, the Ti layer is sputter deposited from a relatively pure titanium target onto the exposed semiconductor wafer. After Ti has been deposited, TiN is sputter deposited upon the Ti-covered semiconductor wafer usually from a titanium target within a nitrogen ambient. Formation of Ti and TiN layers thereby involves dual sputter chambers. Further, sputter deposited TiN introduces large quantities of contaminants during the sputter operation. Generally speaking, sputter-deposited TiN diffusion barrier produces a brittle thin film with poor adhesion to the sputtering system components. A large number of particles are thereby generated during the sputter process which results in a significant increase in deleterious particulate matter deposited upon the wafer.
To avoid sputter downtime and to enhance wafer throughput, many researchers have discovered the advantages of a single sputter deposition step, wherein Ti is sputter deposited, and TiN is formed therefrom. Specifically, TiN can be formed from a Ti layer in one of several ways. First, Ti can be evaporated in a nitrogen ambient. Second, Ti can be reactively sputtered in a nitrogen-bearing gas ambient. Third, Ti can be sputter deposited and thereafter converted to TiN at the Ti exposed surface in a separate plasma nitridation step. Conversion of Ti to TiN according to the third process sequence presents an advantage in that Ti can be converted to TiN simultaneous with conversion of Ti to titanium silicide (TiSi.sub.x) at opposing surfaces of the Ti layer. Thus, nitridation of the Ti layer occurs at a high temperature necessary to produce a TiN passive barrier at the Ti upper surface during silicidation at the Ti lower surface (i.e., at the Ti-semiconductor wafer interface).
Ti nitridation and silicidation can advantageously be performed by rapid thermal heating, sometimes called "rapid thermal annealing" (RTA). The problem inherent in nitridation and silicidation is the competing nature of silicon and nitrogen ingress into the Ti film. As described in Farahani, et al. "A Study of Electrical, Metallurgical, and Mechanical Behaviors of Rapid Thermal Process Ti Films in NH.sub.3 ", Journal of Electrochemical Society, Vol. 141, No. 2, February, 1994 (herein incorporated by reference), a more complete nitridation of Ti is sometimes preempted by the growing silicide layer underneath the growing TiN. Thus, TiN layers formed during a single RTA cycle, which simultaneously forms TiSi.sub.x, are quite thin. An RTA temperature of 700.degree. C. necessary to form TiSi.sub.x will form predominately TiSi.sub.x instead of TiN, even through RTA is performed in a nitrogen ambient. This result is especially true when performed in a pure N.sub.2 ambient. N.sub.2 generally requires a much higher temperature to segregate and form TiN, and therefore, in the meantime, a disproportionate amount of TiSi.sub.x will be formed. The small amount of TiN will not be sufficient to produce a proper passive barrier structure, as described in the immediately preceding article. A thin TiN diffusion barrier (i.e., less than 200 Angstroms) produces unacceptably high junction leakage current and unacceptably low breakdown voltage. The problem is less prevalent in As implant junctions of n-type circuits. It appears the As implants reduce the rate of TiSi.sub.x phase formation by impeding the diffusion of Si into the Ti film. Thus, a larger amount of TiN can form over n-type junctions. The problem is, however, more prevalent in p-type junctions since B or BF.sub.x impurities do not produce the same silicide-reducing effect as As impurities. Therefore, over p-type junctions of, for example, 140.times.70 .mu.m.sup.2 having B concentration of 7.times.10.sup.16 atoms/cm.sup.3, a breakdown voltage of less than 12 volts may occur.
To produce an optimal metallization scheme, the TiN layer must not only be thick in regions overlying p-type junctions, but also the TiN/Ti/TiSi.sub.x tri-layer must have strong adhesion to the underlying junction. In many instances, the TiN/Ti/TiSi.sub.x tri-layer acts as a "glue layer". The tri-layer is interposed between a subsequently placed "plug-layer" and the junction region of a semiconductor surface. Thus, the tri-layer serves to adhere the junction to an overlying plug layer, a suitable plug consists essentially of tungsten (W) material. The W plug is typically CVD formed across the semiconductor wafer and especially in the relatively deep contact holes overlying junction regions. After filling the holes, W is etched back to present a more planar upper surface upon which subsequent dielectrics and metallization levels can be placed. A problem inherent in the juncture between the tri-layer or glue layer and the W plug layer is the stress formed therein. The stress is primarily caused by dissimilar coefficients of thermal expansion between each layer. As described in Farahani et al., "Conventional Contact Interconnect Technology as an Alternative to Contact Plug (W) Technology for 0.485 .mu.m CMOS EPROM IC Devices", IEEE Trans on Semiconductor Manufacturing, Vol. 17, No. 1, February 1994, the tensile stress associated with W film causes the W film to shrink during deposition. W film shrinkage is volumetric and has been shown to cause peeling at the interface between the dielectric and the TiN/Ti structure. Thus, peeling occurs primarily in the interface between Ti portion of the TiN/Ti/TiSi.sub.x glue layer and the dielectric. It is postulated that the cause of poor adherence to the dielectric is primarily due to the relative absence of a metallurgical interaction between TiN/Ti layer and the underlying dielectric.
It would therefore be advantageous to derive a fabrication process which optimizes the properties of the multi-layered metallization contact structure. Specifically, the contact structure must be formed using a single sputter deposition step and, more importantly, the Ti film defined in the junction region must be of a certain minimum thickness. Moreover, the TiN layer formed from the Ti film must be of a certain minimum thickness. Still further, the TiN/Ti/TiSi.sub.x glue layer must have excellent adherence in regions where adherence is oftentimes a problem. The derived fabrication methodology must therefore be capable of converting the lower portions of the ensuing tri-layer structure to a sufficiently thick TiSi.sub.x layer in regions where silicon is less prevalent (i.e., in the dielectric regions overlying the silicon substrate). Absent a relatively thick TiSi.sub.x, tensile stress from overlying W plug layer will deleteriously contract and peel the glue layer away from the dielectric.